173 search results - page 13 / 35 » Low power and low voltage CMOS digital circuit techniques |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
A high-to-low switching DC-DC converter that operates at input supply voltages up to two times as high as the maximum voltage permitted in a nanometer CMOS technology is proposed ...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
This paper presents a novel technique to mitigate effects of datapath and memory errors in JPEG implementations. These errors are mainly caused by voltage scaling and process vari...
ISCAS
2011
IEEE
12 years 11 months ago
2011
IEEE
—A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an a...
DATE
2010
IEEE
14 years 25 days ago
2010
IEEE
—In this paper we study the effectiveness of two power gating methods – transistor switches and MEMS switches – in reducing the power consumption of a design with a certain t...
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...