173 search results - page 14 / 35 » Low power and low voltage CMOS digital circuit techniques |
CCECE
2006
IEEE
14 years 1 months ago
2006
IEEE
A high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for liquid crystal display applications, is proposed. The summing circuit is biased by the constant...
SBCCI
2006
ACM
14 years 1 months ago
2006
ACM
The design of a low-power differential switched-capacitor amplifier for processing a fully-differential input signal coming from a pressure sensor interface is reported. The circu...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a g...
TVLSI
2011
13 years 2 months ago
2011
—A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional ...
TVLSI
2002
13 years 7 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...