173 search results - page 24 / 35 » Low power and low voltage CMOS digital circuit techniques |
DDECS
2009
IEEE
14 years 2 months ago
2009
IEEE
– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
A technique for evaluating noise figure suitable for BIST implementation is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of ...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— An overview of digital enhancement techniques for analog circuits is presented. Recent research suggests that the high density and low energy of digital circuits can be leverag...
ASYNC
2006
IEEE
14 years 1 months ago
2006
IEEE
Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...