173 search results - page 6 / 35 » Low power and low voltage CMOS digital circuit techniques |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper presents a two-stage CMOS differential voltage-controlled ring oscillator (VCO). The VCO is intended to operate as a frequency synthesizer in a PLL to generate local os...
ICCD
2000
IEEE
14 years 3 days ago
2000
IEEE
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
DATE
2010
IEEE
14 years 24 days ago
2010
IEEE
— This work presents a High-Voltage Low-Power CMOS DC-DC buck regulator for automotive applications. The overall system, including the high and low voltage analog devices, the po...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...