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» Low power architecture of the soft-output Viterbi algorithm
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NOCS
2007
IEEE
14 years 29 days ago
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...
ARITH
2005
IEEE
14 years 10 days ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
IJRR
2006
171views more  IJRR 2006»
13 years 6 months ago
The Cobotic Hand Controller: Design, Control and Performance of a Novel Haptic Display
We examine the design, control and performance of the Cobotic Hand Controller, a novel, six-degree-of-freedom, admittance controlled haptic display. A highly geared admittance arch...
Eric L. Faulring, J. Edward Colgate, Michael A. Pe...
VLSID
2006
IEEE
240views VLSI» more  VLSID 2006»
14 years 7 months ago
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal process...
Venkataraman Mahalingam, N. Ranganathan
DAC
2010
ACM
13 years 10 months ago
A probabilistic and energy-efficient scheduling approach for online application in real-time systems
This work considers the problem of minimizing the power consumption for real-time scheduling on processors with discrete operating modes. We provide a model for determining the ex...
Thorsten Zitterell, Christoph Scholl