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» Low power architecture of the soft-output Viterbi algorithm
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ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
14 years 19 days ago
Low power block based FIR filtering cores
— The authors present a number of complete cores which are specially tailored for the low power implementation of FIR filters executed using block processing. The paper reveals t...
Ahmet T. Erdogan, Tughrul Arslan
CODES
2001
IEEE
13 years 11 months ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue
SC
2005
ACM
14 years 27 days ago
ClawHMMER: A Streaming HMMer-Search Implementation
The proliferation of biological sequence data has motivated the need for an extremely fast probabilistic sequence search. One method for performing this search involves evaluating...
Daniel Reiter Horn, Mike Houston, Pat Hanrahan
CODES
2004
IEEE
13 years 11 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
DAC
2007
ACM
14 years 8 months ago
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
Lei Cheng, Deming Chen, Martin D. F. Wong