331 search results - page 16 / 67 » Low power implementation of a turbo-decoder on programmable ... |
157
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IPPS
2010
IEEE
15 years 3 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
118
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VLSID
2006
IEEE
16 years 6 months ago
2006
IEEE
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
157
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of ...
144
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ESCIENCE
2006
IEEE
15 years 12 months ago
2006
IEEE
This paper introduces the concept of a User Programmable Virtualized Network, which allows networks to deliver application specific services using network element components that ...
148
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DSD
2007
IEEE
16 years 5 days ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...