331 search results - page 26 / 67 » Low power implementation of a turbo-decoder on programmable ... |
198
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DEBS
2010
ACM
15 years 9 months ago
2010
ACM
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
168
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ISCA
2006
IEEE
15 years 12 months ago
2006
IEEE
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
168
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FCCM
2000
IEEE
15 years 10 months ago
2000
IEEE
Simplifying the programming models is paramount to the success of reconfigurable computing. We apply the principles of object-oriented programming to the design of stream archite...
166
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
144
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FCCM
1999
IEEE
15 years 10 months ago
1999
IEEE
We have implemented an image combining architecture that allows distributed rendering of a partitioned data set at interactive rates. The architecture achieves real-time frame rat...