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FPL
2007
Springer
100views Hardware» more  FPL 2007»
16 years 2 days ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
16 years 7 days ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
CODES
2005
IEEE
15 years 11 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
CACM
2000
158views more  CACM 2000»
15 years 5 months ago
Wireless Integrated Network Sensors
Wireless Integrated Network Sensors (WINS) now provide a new monitoring and control capability for transportation, manufacturing, health care, environmental monitoring, and safety...
Gregory J. Pottie, William J. Kaiser
AFRICACRYPT
2010
Springer
16 years 12 days ago
Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices
The market for RFID technology has grown rapidly over the past few years. Going along with the proliferation of RFID technology is an increasing demand for secure and privacy-prese...
Marcel Medwed, François-Xavier Standaert, J...