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ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
15 years 11 months ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
16 years 20 days ago
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
—The IEEE 802.15.4a amendment has introduced ultra-wideband impulse radio (UWB IR) as a promising physical layer for energy-efficient, low data rate communications. A critical p...
Christian Bachmann, Andreas Genser, Jos Hulzink, M...
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
15 years 12 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
ICASSP
2011
IEEE
14 years 9 months ago
Design and implementation of cubic spline interpolation for spike sorting microsystems
Abstract—Accurate spike sorting is important for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural wavefo...
Tung-Chien Chen, Yun-Yu Chen, Tsung-Chuan Ma, Lian...
DAC
2005
ACM
15 years 7 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes