331 search results - page 40 / 67 » Low power implementation of a turbo-decoder on programmable ... |
160
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DAC
2004
ACM
16 years 6 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
145
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MAM
2002
15 years 5 months ago
2002
The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeline...
146
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ISLPED
2005
ACM
15 years 11 months ago
2005
ACM
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
174
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ISCA
2008
IEEE
15 years 5 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
136
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ERSA
2006
15 years 7 months ago
2006
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...