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APCSAC
2006
IEEE
15 years 11 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
DELTA
2006
IEEE
15 years 9 months ago
Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder
The efficiency of the Public Key encryption systems like RSA and ECC can be improved with the adoption of a faster multiplication scheme. In this paper, Modified Montgomery multip...
Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Redd...
DAC
2004
ACM
16 years 6 months ago
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding
This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption using the computational workload decomposition. Th...
Kihwan Choi, Ramakrishna Soma, Massoud Pedram
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
16 years 11 days ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
ICPP
2006
IEEE
15 years 11 months ago
Parallel Algorithms for Evaluating Centrality Indices in Real-world Networks
This paper discusses fast parallel algorithms for evaluating several centrality indices frequently used in complex network analysis. These algorithms have been optimized to exploi...
David A. Bader, Kamesh Madduri