Sciweavers

331 search results - page 6 / 67
» Low power implementation of a turbo-decoder on programmable ...
Sort
View
ISCAS
2005
IEEE
159views Hardware» more  ISCAS 2005»
15 years 11 months ago
A low power FPGA routing architecture
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...
Somsubhra Mondal, Seda Ogrenci Memik
IPPS
2006
IEEE
15 years 11 months ago
Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
Panagiotis D. Michailidis, Konstantinos G. Margari...
ICASSP
2011
IEEE
14 years 9 months ago
Fixed- versus floating-point implementation of MIMO-OFDM detector
In this paper, we investigate the opportunities offered by floatingpoint arithmetics in enabling an assembly and intrinsics free highlevel language based development. We compare ...
Janne Janhunen, Perttu Salmela, Olli Silvén...
FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
15 years 11 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
VLSID
2007
IEEE
99views VLSI» more  VLSID 2007»
16 years 6 months ago
Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...