331 search results - page 7 / 67 » Low power implementation of a turbo-decoder on programmable ... |
173
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FPL
2008
Springer
15 years 7 months ago
2008
Springer
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconf...
162
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GLOBECOM
2007
IEEE
15 years 7 months ago
2007
IEEE
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...
119
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
118
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DATE
2008
IEEE
16 years 6 days ago
2008
IEEE
This paper presents the design and the laboratory results of an integrated half-bridge driver for power electronic systems in a 0.35 µm Bipolar CMOS DMOS (BCD) technology. The pr...
146
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VLSID
2006
IEEE
16 years 6 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...