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VLSID
2009
IEEE
108views VLSI» more  VLSID 2009»
14 years 9 months ago
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Forrest Brewer, João Pedro Hespanha, Nitin ...
DATE
2004
IEEE
151views Hardware» more  DATE 2004»
14 years 14 days ago
Dynamic Voltage and Cache Reconfiguration for Low Power
Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requi...
André C. Nácul, Tony Givargis
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 9 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
JCP
2008
160views more  JCP 2008»
13 years 8 months ago
A Bluetooth-based Sensor Node for Low-Power Ad Hoc Networks
TCP/IP has recently taken promising steps toward being a viable communication architecture for networked sensor nodes. Furthermore, the use of Bluetooth can enable a wide range of ...
Jens Eliasson, Per Lindgren, Jerker Delsing
EMSOFT
2007
Springer
14 years 2 months ago
Block recycling schemes and their cost-based optimization in nand flash memory based storage system
Flash memory has many merits such as light weight, shock resistance, and low power consumption, but also has limitations like the erase-before-write property. To overcome such lim...
Jongmin Lee, Sunghoon Kim, Hunki Kwon, Choulseung ...