82 search results - page 13 / 17 » Low power logic synthesis for XOR based circuits |
CHES
2005
Springer
14 years 28 days ago
2005
Springer
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
DFT
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
DSD
2006
IEEE
13 years 9 months ago
2006
IEEE
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...