97 search results - page 10 / 20 » Low power network processor design using clock gating |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
: In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. Th...
TVLSI
1998
13 years 7 months ago
1998
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
JCP
2007
13 years 7 months ago
2007
—Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, a...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...