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» Low power network processor design using clock gating
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FPGA
2008
ACM
151views FPGA» more  FPGA 2008»
13 years 9 months ago
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
Michael T. Frederick, Arun K. Somani
DAC
2002
ACM
14 years 8 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
SIGCOMM
2009
ACM
14 years 2 months ago
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Est...
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
14 years 2 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
14 years 2 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim