21 search results - page 4 / 5 » Low power sequential circuit design by using priority encodi... |
HPCA
2012
IEEE
12 years 3 months ago
2012
IEEE
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
TVLSI
1998
13 years 7 months ago
1998
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
TVLSI
2010
13 years 2 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...