21 search results - page 4 / 5 » Low power sequential circuit design by using priority encodi... |
172
Voted
HPCA
2012
IEEE
14 years 28 days ago
2012
IEEE
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
159
Voted
DAC
2005
ACM
15 years 7 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
132
Voted
ISLPED
2009
ACM
15 years 12 months ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
158
click to vote
TVLSI
1998
15 years 5 months ago
1998
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
177
Voted
TVLSI
2010
15 years 1 days ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...