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» Low power techniques for Motion Estimation hardware
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DSD
2009
IEEE
147views Hardware» more  DSD 2009»
13 years 11 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu
ASPDAC
2001
ACM
117views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Low power techniques for address encoding and memory allocation
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (be...
Wei-Chung Cheng, Massoud Pedram
IWSOC
2005
IEEE
141views Hardware» more  IWSOC 2005»
14 years 1 months ago
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
Kenneth A. Townsend, James W. Haslett, Krzysztof I...
JEI
2000
133views more  JEI 2000»
13 years 7 months ago
Low complexity block motion estimation using morphological-based feature extraction and XOR operations
Motion estimation is a temporal image compression technique, where an n x n block of pixels in the current frame of a video sequence is represented by a motion vector with respect...
Thinh M. Le, R. Mason, Sethuraman Panchanathan
DSD
2007
IEEE
164views Hardware» more  DSD 2007»
14 years 2 months ago
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation
In this paper, we present an efficient hardware architecture for real-time implementation of quarter-pixel accurate variable block size motion estimation for H.264 / MPEG4 Part 10...
Serkan Oktem, Ilker Hamzaoglu