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    VLSID
    2002
    IEEE
    207views VLSI» more  VLSID 2002»
    Synthesis of High Performance Low Power Dynamic CMOS Circuits
    14 years 7 months ago
    Synthesis of High Performance Low Power Dynamic CMOS Circuits
    Download  www.cs.cmu.edu
    This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
    Debasis Samanta, Nishant Sinha, Ajit Pal
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    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 8 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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    DAC
    1999
    ACM
    149views Computer Architecture» more  DAC 1999»
    Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
    13 years 11 months ago
    Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
    Download  www.cecs.uci.edu
    Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
    Vijay Sundararajan, Keshab K. Parhi
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    DATE
    2005
    IEEE
    154views Hardware» more  DATE 2005»
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
    14 years 22 days ago
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
    Download  infoscience.epfl.ch
    We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
    Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...
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    ISQED
    2000
    IEEE
    131views Hardware» more  ISQED 2000»
    Low Power Testing of VLSI Circuits: Problems and Solutions
    13 years 11 months ago
    Low Power Testing of VLSI Circuits: Problems and Solutions
    Download  dit.upc.es
    Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
    Patrick Girard
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