10 search results - page 2 / 2 » Lowering Error Floor of LDPC Codes Using a Joint Row-Column ... |
JSAC
2010
13 years 5 months ago
2010
Abstract— There is a well-known error-floor phenomenon associated with iterative LDPC decoders which has delayed the use of LDPC codes in certain communication and storage syste...
CORR
2006
Springer
13 years 7 months ago
2006
Springer
The asymptotic iterative decoding performances of low-density parity-check (LDPC) codes using min-sum (MS) and sum-product (SP) decoding algorithms on memoryless binary-input outp...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
CISS
2008
IEEE
14 years 1 months ago
2008
IEEE
—The error floor of bit-interleaved coded modulation with iterative decoding (BICM-ID) can be minimized for a particular constellation by maximizing the harmonic mean of the squ...
ICC
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—We consider non-asymmetric distributed source coding (DSC) that achieves any point in the Slepian-Wolf (SW) region. We study the error propagation phenomena and propose ...