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ARITH
1993
IEEE
13 years 11 months ago
An accurate LNS arithmetic unit using interleaved memory function interpolator
This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage...
David M. Lewis
ARC
2006
Springer
120views Hardware» more  ARC 2006»
13 years 11 months ago
Applications of Small-Scale Reconfigurability to Graphics Processors
We explore the application of Small-Scale Reconfigurability (SSR) to graphics hardware. SSR is an architectural technique wherein functionality common to multiple subunits is reuse...
Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, ...
ICC
2011
IEEE
237views Communications» more  ICC 2011»
12 years 7 months ago
Reorganized and Compact DFA for Efficient Regular Expression Matching
—Regular expression matching has become a critical yet challenging technique in content-aware network processing, such as application identification and deep inspection. To meet ...
Kai Wang, Yaxuan Qi, Yibo Xue, Jun Li
ISCAS
2008
IEEE
85views Hardware» more  ISCAS 2008»
14 years 1 months ago
Frame-parallel design strategy for high definition B-frame H.264/AVC encoder
High Definition (HD) H.264/AVC video compression is the emerging necessity on nowadays home entertainment environment and so on. However, Although B-frame coding scheme provides ...
Yi-Hau Chen, Tzu-Der Chuang, Yu-Han Chen, Chen-Han...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...