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ICCD
2002
IEEE
88views Hardware» more  ICCD 2002»
14 years 4 months ago
Improving Processor Performance by Simplifying and Bypassing Trivial Computations
During the course of a program’s execution, a processor performs many trivial computations; that is, computations that can be simplified or where the result is zero, one, or equ...
Joshua J. Yi, David J. Lilja
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
14 years 1 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
13 years 11 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
FCCM
2005
IEEE
107views VLSI» more  FCCM 2005»
14 years 1 months ago
Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller
As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. To reduce design time for new products, the reuse o...
Lesley Shannon, Paul Chow
DSD
2010
IEEE
110views Hardware» more  DSD 2010»
13 years 7 months ago
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour
—The design of new embedded systems is getting more and more complex as more functionality is integrated into these systems. To deal with the design complexity, a predictable des...
Sander Stuijk, Marc Geilen, Twan Basten