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GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
14 years 9 days ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
VTS
2002
IEEE
109views Hardware» more  VTS 2002»
14 years 7 days ago
Controlling Peak Power During Scan Testing
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
Ranganathan Sankaralingam, Nur A. Touba
JGTOOLS
2008
126views more  JGTOOLS 2008»
13 years 7 months ago
Simple Empty-Space Removal for Interactive Volume Rendering
Interactive volume rendering methods such as texture-based slicing techniques and ray-casting have been well developed in recent years. The rendering performance is generally restr...
Vincent Vidal 0002, Xing Mei, Philippe Decaudin
MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
14 years 1 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm