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DAC
2010
ACM
13 years 10 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
DATE
2010
IEEE
149views Hardware» more  DATE 2010»
14 years 2 months ago
Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems
—As Electronic Control Units (ECUs) and embedded software functions within an automobile keep increasing in number, the scale and complexity of automotive embedded systems is gro...
Karthik Lakshmanan, Gaurav Bhatia, Ragunathan Rajk...
SAC
2006
ACM
14 years 3 months ago
Hardware/software 2D-3D backprojection on a SoPC platform
The reduction of image reconstruction time is needed to spread the use of PET for research and routine clinical practice. In this purpose, this article presents a hardware/softwar...
Nicolas Gac, Stéphane Mancini, Michel Desvi...
EMSOFT
2007
Springer
14 years 4 months ago
Loosely time-triggered architectures based on communication-by-sampling
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
Albert Benveniste, Paul Caspi, Marco Di Natale, Cl...
RTAS
2008
IEEE
14 years 4 months ago
Bounding Worst-Case Response Time for Tasks with Non-Preemptive Regions
Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a schedu...
Harini Ramaprasad, Frank Mueller