44 search results - page 6 / 9 » MOS VLSI circuit simulation by hardware accelerator using se... |
PATMOS
2005
Springer
14 years 2 months ago
2005
Springer
As the number of metal layers and the frequency of VLSI continue to increase, the voltage droop on both the package and vias is becoming more pronounced. This paper analyzes the nu...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
—In this paper, we present an approach to nonlinear model reduction based on representing a nonlinear system with a piecewise-linear system and then reducing each of the pieces w...
ICCD
1997
IEEE
14 years 22 days ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
APIN
2002
13 years 8 months ago
2002
This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the infer...