As the number of metal layers and the frequency of VLSI continue to increase, the voltage droop on both the package and vias is becoming more pronounced. This paper analyzes the nu...
Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Ta...
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
—In this paper, we present an approach to nonlinear model reduction based on representing a nonlinear system with a piecewise-linear system and then reducing each of the pieces w...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the infer...