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ASAP
2006
IEEE
111views Hardware» more  ASAP 2006»
14 years 4 months ago
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
Yedidya Hilewitz, Ruby B. Lee
ISCAS
2006
IEEE
103views Hardware» more  ISCAS 2006»
14 years 4 months ago
A low-power geometric mapping co-processor for high-speed graphics application
Abstract— In this article we present a novel design of a lowpower geometric mapping co-processor that can be used for high-performance graphics system. The processor can carry ou...
S. Leeke, L. Maharatna
ASAP
2005
IEEE
182views Hardware» more  ASAP 2005»
14 years 3 months ago
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
Tom R. Jacobs, José L. Núñez-...
GRAPHITE
2005
ACM
14 years 3 months ago
A loose and sketchy approach in a mediated reality environment
In this paper, we present sketchy-ar-us, a modified, real-time version of the Loose and Sketchy algorithm used to render graphics in an AR environment. The primary challenge was ...
Michael Haller, Florian Landerl, Mark Billinghurst
GECCO
2005
Springer
121views Optimization» more  GECCO 2005»
14 years 3 months ago
New evolutionary techniques for test-program generation for complex microprocessor cores
Checking if microprocessor cores are fully functional at the end of the productive process has become a major issue. Traditional functional approaches are not sufficient when cons...
Ernesto Sánchez, Massimiliano Schillaci, Ma...