Sciweavers

877 search results - page 112 / 176
» MXQuery with Hardware Acceleration
Sort
View
124
Voted
DAC
2005
ACM
16 years 3 months ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
117
Voted
ISCA
2007
IEEE
149views Hardware» more  ISCA 2007»
15 years 8 months ago
An effective hybrid transactional memory system with strong isolation guarantees
We propose signature-accelerated transactional memory (SigTM), a hybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the r...
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Au...
SI3D
1992
ACM
15 years 6 months ago
Interactive Volume Rendering on a Multicomputer
Direct volume rendering is a computationally intensive operation that has become a valued and often preferred visualization tool. For maximal data comprehension, interactive manip...
Ulrich Neumann
87
Voted
ICCAD
2006
IEEE
117views Hardware» more  ICCAD 2006»
15 years 11 months ago
Post-routing redundant via insertion and line end extension with via density consideration
- Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. Ho...
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
134
Voted
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
15 years 8 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...