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ICCD
1994
IEEE
157views Hardware» more  ICCD 1994»
14 years 2 months ago
Mesh Routing Topologies for Multi-FPGA Systems
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a sy...
Scott Hauck, Gaetano Borriello, Carl Ebeling
ASPDAC
2007
ACM
80views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Recognition of Fanout-free Functions
Factoring is a logic minimization technique to represent a Boolean function in an equivalent function with minimum literals. When realizing the circuit, a function represented in ...
Tsung-Lin Lee, Chun-Yao Wang
FPL
2009
Springer
132views Hardware» more  FPL 2009»
14 years 1 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
FPL
2006
Springer
119views Hardware» more  FPL 2006»
14 years 1 months ago
The Entropy of FPGA Reconfiguration
In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propos...
Usama Malik, Oliver Diessel
ASAP
2008
IEEE
119views Hardware» more  ASAP 2008»
13 years 12 months ago
An FPGA architecture for CABAC decoding in manycore systems
Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arith...
Roberto R. Osorio, Javier D. Bruguera