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113
Voted
ASAP
2008
IEEE
117views Hardware» more  ASAP 2008»
15 years 4 months ago
Reconfigurable acceleration of microphone array algorithms for speech enhancement
Microphone arrays play an important role in noise reduction and speech enhancement. Their algorithms are based on beamforming, which reduces the level of localized and ambient noi...
Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao...
101
Voted
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
15 years 6 months ago
Efficient On-Chip Communications for Data-Flow IPs
We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their ion in a system on chip. We abstract the communication behaviour of the data flow IP so a...
Antoine Fraboulet, Tanguy Risset
97
Voted
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 6 months ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
102
Voted
IEEEPACT
2009
IEEE
15 years 9 months ago
Quantifying the Potential of Program Analysis Peripherals
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...
Mohit Tiwari, Shashidhar Mysore, Timothy Sherwood
131
Voted
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
15 years 4 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...