20 search results - page 2 / 4 » Mach on a Virtually Addressed Cache Architecture |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such prolif...
ICPP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current twodimensional (2...