39 search results - page 2 / 8 » Macro-driven circuit design methodology for high-performance... |
ISQED
2000
IEEE
2000
IEEE
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
14 years 3 days ago
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
ARVLSI
2001
IEEE
13 years 11 months ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...