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ICCAD
2001
IEEE
86views Hardware» more  ICCAD 2001»
14 years 4 months ago
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
Tony Givargis, Frank Vahid, Jörg Henkel
ISCC
2005
IEEE
120views Communications» more  ISCC 2005»
14 years 1 months ago
Modular Reference Implementation of an IP-DSLAM
We describe a modular reference implementation of an IPbased DSL access multiplexer (DSLAM). We identify deployment trends and primary tasks a future DSLAM has to offer. The imple...
Christian Sauer, Matthias Gries, Sören Sonnta...
CVPR
2007
IEEE
14 years 9 months ago
Biased Manifold Embedding: A Framework for Person-Independent Head Pose Estimation
The estimation of head pose angle from face images is an integral component of face recognition systems, human computer interfaces and other human-centered computing applications....
Vineeth Nallure Balasubramanian, Jieping Ye, Sethu...
ICCCN
2007
IEEE
14 years 1 months ago
Lagniappe: Multi-* Programming Made Simple
—The emergence of multi-processor, multi-threaded architectures (referred to as multi- architectures) facilitates the design of high-throughput request processing systems (e.g., ...
Taylor L. Riché, R. Greg Lavender, Harrick ...
CODES
2004
IEEE
13 years 11 months ago
A novel deadlock avoidance algorithm and its hardware implementation
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
Jaehwan Lee, Vincent John Mooney III