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» Mapping Applications to a Coarse Grain Reconfigurable System
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DATE
2009
IEEE
242views Hardware» more  DATE 2009»
14 years 3 months ago
A high performance reconfigurable Motion Estimation hardware architecture
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...
Ozgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilk...
CGA
2008
13 years 8 months ago
Interactive Reconfiguration of Urban Layouts
The ability to create and edit a model of a large-scale city is necessary for a variety of applications such as web-based navigation (e.g., MapQuest, GoogleEarth), emergency respo...
Daniel G. Aliaga, Bedrich Benes, Carlos A. Vanegas...
CODES
2010
IEEE
13 years 5 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...
DAC
2004
ACM
14 years 8 days ago
An SoC design methodology using FPGAs and embedded microprocessors
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
Nobuyuki Ohba, Kohji Takano
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
14 years 2 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman