85 search results - page 3 / 17 » Mapping Interconnection Networks into VEDIC Networks |
154
click to vote
CODES
2003
IEEE
15 years 8 months ago
2003
IEEE
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
110
Voted
ASPDAC
2010
ACM
15 years 1 months ago
2010
ACM
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
119
Voted
EUROPAR
2009
Springer
15 years 10 months ago
2009
Springer
Optimal network performance is critical to efficient parallel scaling for communication-bound applications on large machines. With wormhole routing, no-load latencies do not increa...
124
click to vote
SLIP
2009
ACM
15 years 9 months ago
2009
ACM
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
155
Voted
HPCC
2011
Springer
14 years 3 months ago
2011
Springer
— Mapping of parallel applications on the network topology is becoming increasingly important on large supercomputers. Topology aware mapping can reduce the hops traveled by mess...