66 search results - page 9 / 14 » Masking timing errors on speed-paths in logic circuits |
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
ITC
2003
IEEE
14 years 22 days ago
2003
IEEE
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
TCAD
2008
13 years 7 months ago
2008
Abstract--Designers and high-level synthesis tools can introduce unwanted cycles in digital circuits, and for certain combinational functions, cyclic circuits that are stable and d...