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» Massively parallel processing on a chip
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ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 2 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
ASPLOS
1996
ACM
13 years 11 months ago
The Case for a Single-Chip Multiprocessor
Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we l...
Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ke...
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 11 months ago
Communication Analysis for System-On-Chip Design
In this paper we present an approach for analysis of systems of parallel, communicating processes for SoC design. We present a method to detect communications that synchronize the...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
IEEEHPCS
2010
13 years 6 months ago
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms a...
Shivani Raghav, Martino Ruggiero, David Atienza, C...
CORR
2010
Springer
135views Education» more  CORR 2010»
13 years 7 months ago
Gravitational tree-code on graphics processing units: implementation in CUDA
We present a new very fast tree-code which runs on massively parallel Graphical Processing Units (GPU) with NVIDIA CUDA architecture. The tree-construction and calculation of mult...
Evghenii Gaburov, Jeroen Bédorf, Simon Port...