391 search results - page 31 / 79 » Massively parallel processing on a chip |
FPL
2008
Springer
13 years 9 months ago
2008
Springer
We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use t...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to wh...
HPCA
2000
IEEE
14 years 13 hour ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
SIGARCH
2008
13 years 7 months ago
2008
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...