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ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
JSAC
2006
124views more  JSAC 2006»
13 years 9 months ago
A game-theoretic approach to energy-efficient power control in multicarrier CDMA systems
A game-theoretic model for studying power control in multicarrier code-division multiple-access systems is proposed. Power control is modeled as a noncooperative game in which each...
Farhad Meshkati, Mung Chiang, H. Vincent Poor, Stu...
ANCS
2008
ACM
13 years 11 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
DAC
1998
ACM
14 years 1 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
14 years 2 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...