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ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
14 years 2 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
13 years 11 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
PODC
1995
ACM
13 years 11 months ago
A Framework for Protocol Composition in Horus
The Horus system supports a communication architecture ats protocols as instances of an abstract data type. This approach encourages developers to partition complex protocols into...
Robbert van Renesse, Kenneth P. Birman, Roy Friedm...
JEI
2000
133views more  JEI 2000»
13 years 7 months ago
Low complexity block motion estimation using morphological-based feature extraction and XOR operations
Motion estimation is a temporal image compression technique, where an n x n block of pixels in the current frame of a video sequence is represented by a motion vector with respect...
Thinh M. Le, R. Mason, Sethuraman Panchanathan
PODC
2000
ACM
13 years 11 months ago
Efficient atomic broadcast using deterministic merge
We present an approach for merging message streams from producers distributed over a network, using a deterministic algorithm that is independent of any nondeterminism of the syst...
Marcos Kawazoe Aguilera, Robert E. Strom