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NIPS
1997
13 years 9 months ago
A 1, 000-Neuron System with One Million 7-bit Physical Interconnections
An asynchronous PDM (Pulse-Density-Modulating) digital neural network system has been developed in our laboratory. It consists of one thousand neurons that are physically intercon...
Yuzo Hirai
PDP
2010
IEEE
14 years 15 days ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
14 years 9 days ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain
DATE
2010
IEEE
144views Hardware» more  DATE 2010»
14 years 1 months ago
A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation
—Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low comput...
Abdulkadir Akin, G. Sayilar, Ilker Hamzaoglu
SIGMETRICS
1998
ACM
13 years 7 months ago
Scheduling with Implicit Information in Distributed Systems
Implicitcoscheduling is a distributed algorithm fortime-sharing communicating processes in a cluster of workstations. By observing and reacting to implicit information, local sche...
Andrea C. Arpaci-Dusseau, David E. Culler, Alan M....