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FCCM
2006
IEEE
108views VLSI» more  FCCM 2006»
14 years 1 months ago
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism
This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This...
Charles L. Cathey, Jason D. Bakos, Duncan A. Buell
ICDCS
2002
IEEE
14 years 21 days ago
ControlWare: A Middleware Architecture for Feedback Control of Software Performance
Attainment of software performance assurances in open, largely unpredictable environments has recently become an important focus for real-time research. Unlike closed embedded sys...
Ronghua Zhang, Chenyang Lu, Tarek F. Abdelzaher, J...
HPCN
1997
Springer
13 years 12 months ago
Performance Evaluation of HPCN Applications
The performance attained by parallel programs executed on multiprocessor systems is largely in uenced both by the characteristics of the code and by those of the system architectu...
Alessandro P. Merlo
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
14 years 8 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
HPCA
2000
IEEE
14 years 5 days ago
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620
The paper presents PowerMANNA - a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophi...
Peter M. Behr, S. Pletner, Angela C. Sodan