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IEEEHPCS
2010
13 years 6 months ago
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms a...
Shivani Raghav, Martino Ruggiero, David Atienza, C...
HIPC
1999
Springer
14 years 1 days ago
Process Migration Effects on Memory Performance of Multiprocessor
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Anton...
DSD
2009
IEEE
147views Hardware» more  DSD 2009»
13 years 11 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 2 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
PPOPP
2003
ACM
14 years 1 months ago
Impala: a middleware system for managing autonomic, parallel sensor systems
Sensor networks are long-running computer systems with many sensing/compute nodes working to gather information about their environment, process and fuse that information, and in ...
Ting Liu, Margaret Martonosi