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DAC
2010
ACM
13 years 8 months ago
Performance and power modeling in a multi-programmed multi-core environment
This paper describes a fast, automated technique for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-cor...
Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley M...
CLUSTER
2008
IEEE
13 years 8 months ago
Benchmarking the effects of operating system interference on extreme-scale parallel machines
We investigate operating system noise, which we identify as one of the main reasons for a lack of synchronicity in parallel applications. Using a microbenchmark, we measure the no...
Peter H. Beckman, Kamil Iskra, Kazutomo Yoshii, Su...
CLUSTER
2007
IEEE
14 years 2 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
EUROPAR
2010
Springer
13 years 9 months ago
Optimized Dense Matrix Multiplication on a Many-Core Architecture
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
Elkin Garcia, Ioannis E. Venetis, Rishi Khan, Guan...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 2 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...