4118 search results - page 821 / 824 » Mechanisms for usage control |
TCAD
2010
13 years 2 months ago
2010
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
TCS
2010
13 years 2 months ago
2010
We consider the problem of maximizing the minimum load for machines that are controlled by selfish agents, who are only interested in maximizing their own profit. Unlike the class...
TROB
2010
13 years 2 months ago
2010
The property of form-closure of a grasp, as generally defined in the literature, is based on the assumption that contact points between the hand and the object are fixed in space. ...
TC
2011
13 years 1 months ago
2011
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...