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MICRO
2008
IEEE
79views Hardware» more  MICRO 2008»
13 years 7 months ago
Strategies for mapping dataflow blocks to distributed hardware
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
Behnam Robatmili, Katherine E. Coons, Doug Burger,...
IPPS
2007
IEEE
14 years 1 months ago
Table-lookup based Crossbar Arbitration for Minimal-Routed, 2D Mesh and Torus Networks
Crossbar arbitration—which determines the allocation of output ports to packets in the input queues—is a performance-critical stage in the overall performance of routers for i...
Daeho Seo, Mithuna Thottethodi
ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
14 years 1 months ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...
EACL
2003
ACL Anthology
13 years 9 months ago
Cohesion and coherence for Automatic Summarization
This paper presents the integration of cohesive properties of text with coherence relations, to obtain an adequate representation of text for automatic summarization. A summarizer...
Laura Alonso Alemany, María Fuentes Fort
ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
14 years 4 months ago
An analytical model for negative bias temperature instability
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...