Strategies for mapping dataflow blocks to distributed hardware

Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of dependence chains, and communication penalties. The amount of concurrency determines the importance of the other factors: if concurrency is high, wider distribution of instructions is likely to tolerate the increased operand routing latencies. If concurrency is low, mapping dependent instructions close to one another is likely to reduce communication costs that contribute to the critical path. This paper explores these tradeoffs for distributed Explicit Dataflow Graph Execution (EDGE) architectures that execute blocks of dataflow instructions atomically. A runtime block mapper assigns instructions from a single thread to distributed hardware resources (cores) based on compilerassigned instruction identifiers. We explore two approaches: fixed strategies that map all blocks to the same number of cores, and adaptive ...

• Type: Journal
• Year: 2008
• Where: MICRO
• Authors: Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley
• Keywords: Cores, Hardware, Instruction, MICRO 2008, Runtime Block