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VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 10 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
EUROSYS
2007
ACM
14 years 7 months ago
Latency and bandwidth-minimizing failure detectors
Failure detectors are fundamental building blocks in distributed systems. Multi-node failure detectors, where the detector is tasked with monitoring N other nodes, play a critical...
Kelvin C. W. So, Emin Gün Sirer
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 4 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
RTSS
2008
IEEE
14 years 4 months ago
Rate-Harmonized Scheduling for Saving Energy
—Energy consumption continues to be a major concern in multiple application domains including powerhungry data centers, portable and wearable devices, mobile communication device...
Anthony Rowe, Karthik Lakshmanan, Haifeng Zhu, Rag...
RTSS
2006
IEEE
14 years 3 months ago
Voice over Sensor Networks
Wireless sensor networks have traditionally focused on low duty-cycle applications where sensor data are reported periodically in the order of seconds or even longer. This is due ...
Rahul Mangharam, Anthony Rowe, Raj Rajkumar, Ryohe...