71 search results - page 13 / 15 » Memory Access Coalescing: A technique for Eliminating Redund... |
ISSTA
2009
ACM
14 years 3 months ago
2009
ACM
Dynamic test generation consists of executing a program while gathering symbolic constraints on inputs from predicates encountered in branch statements, and of using a constraint ...
MICRO
1994
IEEE
14 years 20 days ago
1994
IEEE
Numerical applications frequently contain nested loop structures that process large arrays of data. The execution of these loop structures often produces memory preference pattern...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
RTSS
2003
IEEE
14 years 1 months ago
2003
IEEE
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...